周鹏飞, 宗竹林, 肖龙. 一种PON结构航空总线协议芯片的内存架构[J]. 微电子学与计算机, 2013, 30(9): 5-8.
引用本文: 周鹏飞, 宗竹林, 肖龙. 一种PON结构航空总线协议芯片的内存架构[J]. 微电子学与计算机, 2013, 30(9): 5-8.
ZHOU Peng-fei, ZONG Zhu-lin, XIAO Long. The Memory Architecture of PON Structure Avionic Bus Protocol Chip[J]. Microelectronics & Computer, 2013, 30(9): 5-8.
Citation: ZHOU Peng-fei, ZONG Zhu-lin, XIAO Long. The Memory Architecture of PON Structure Avionic Bus Protocol Chip[J]. Microelectronics & Computer, 2013, 30(9): 5-8.

一种PON结构航空总线协议芯片的内存架构

The Memory Architecture of PON Structure Avionic Bus Protocol Chip

  • 摘要: 在分析了基于PON结构的FC-AE总线的基础上,以提高系统传输效率、降低总线功耗为目的,提出了一种使用基于共享存储器和循环存储的数据存储,采取双缓存任务执行机制和内存动态访问控制机制的内存访问方式。软硬件协同测试结果表明,该内存架构具有任务执行效率高,系统交互时间少和动态功耗低的特点。

     

    Abstract: In order to improve the efficiency of the data storage and reduce bus power consumption, a kind of memory architecture with the characteristics of shared storage, circular storage, and global double buffering mechanism has been presented,which is based on the analyses of transmission characteristics of FC -AE bus rely on PON structure.The experimental results show that this architecture has merits of high reliable performance,low delay time and low power dissipation,by testing the co -verification platform with the hardware and software.

     

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