• 北大核心期刊(《中文核心期刊要目总览》来源期刊)
  • 中国科技核心期刊(中国科技论文统计源期刊)
  • JST 日本科学技术振兴机构数据库(日)收录期刊

NoticeMore>

Special TopicMore >

Download CenterMore >

Wechat

Articles just accepted have been peer-reviewed and accepted, which are not yet assigned to volumes /issues, but are citable by Digital Object Identifier (DOI).
Display Method:
Articles in press have been peer-reviewed and accepted, which are not yet assigned to volumes /issues, but are citable by Digital Object Identifier (DOI).
Display Method:
Display Method:
An overview of SRAM in-memory computing
GONG Longqin, XU Weidong, LOU Mian
2021, 38(9): 1-7.  
Abstract(69) HTML(43) PDF (21)
Abstract:
In the process of processing data-intensive applications such as deep neural networks, the frequent transfer of large amounts of data between the processor and the memory causes severe performance loss and energy consumption, which is the biggest bottleneck of the current von Neumann architecture. In view of the limitations of the traditional von Neumann architecture, the SRAM-based in-memory computing technology integrates the computing unit into the memory to support data storage and calculation, which completely breaks through the von Neumann bottleneck and is expected to become a new generation Intelligent computing architecture.This paper clarifies the problems of "power wall" and "storage wall" caused by the von Neumann architecture from the perspective of architecture, and gives the reasons for the rise of in-memory computing. The paper focuses on the research of SRAM-based in-memory computing architectures in recent years, and describes the working mechanism, advantages and disadvantages and significance of various SRAM-based in-memory computing architectures by taking several classical architectures as examples. And from the perspective of device level, circuit level and architecture level, the key factors of current SRAM-based in-memory computing technology are summarized respectively. The SRAM-based in-memory computing technology is a promising and versatile technology that will provide efficient and low-energy system architectures for machine learning applications, graph computing applications and genetic engineering. The paper looks forward to the development of SRAM-based in-memory computing technology in devices, circuits and architectures in the coming year
An object tracking algorithm based on asymmetric residual attention network
CUI Kefan, XIONG Shuhua, Chen Honggang, WU Xiaohong, HE Xiaohai
2021, 38(9): 8-16.  
Abstract(64) HTML(26) PDF (22)
Abstract:
In order to solve the background interference and robustness problems of object tracking algorithm in moving targets, an asymmetric residual attention network algorithm based on Siamese RPN++ was proposed.First, aAsymmetric residual attention structure is added to the network corresponding to the template branch, so as to extract the common features of the sampled images, form a relatively stable target contour, and solve the problem that the target moving background changes.The adaptive weight updating method is adopted to fuse the output features of candidate network modules in different regions to obtain more robust expression of scale change features and solve the problem of target deformation.The experimental results show that the proposed improved algorithm has good tracking accuracy and robustness in challenging tracking test videos, and can deal with the changes of moving background and scale.
Feature extraction of hyperspectral image with spatial-spectral collaboration-competition preserving graph embedding
TAO Yang, WENG Shan, LIN Feipeng, YANG Wen
2021, 38(9): 17-22.  
Abstract(45) HTML(24) PDF (8)
Abstract:
Aiming at the difficulty of labeling hyperspectral image samples and the problem that most feature extraction algorithms only consider spectral feature information but ignore spatial information, a new feature extraction of hyperspectral image with spatial-spectral collaboration-competition preserving graph embedding (SCPGE) in unsupervised scenes was proposed. The collaborative representation is used to characterize the global manifold structure, combined with locality-constrained property based on spatial information and spectral information to calculate the representation coefficient of the pixel. Used the weight matrix of the graph drawn by the coefficient matrix, and the objective function with regular term to obtain the projection matrix. The experimental results on Indian Pines and Salinas hyperspectral data sets show that the proposed method is better than others.
Research on the construction algorithm of measurement matrix based on mixed chaotic
LI Xuezhen, LING Yongfa
2021, 38(9): 23-30.  
Abstract(43) HTML(23) PDF (3)
Abstract:
In order to improve the performance of measurement matrix, an algorithm of measurement matrix construction based on XOR mixed chaotic sequence is proposed. Based on Chebyshev chaotic map and advanced Logistic chaotic mapping, a mathematical model of the mixed chaotic map was proposed. By the method of threshold function, real value quantitative chaotic sequence for binary and real value of chaotic sequence can be converted to binary chaotic sequence.Then the mixed chaotic sequence is obtained by combining the two binary chaotic sequences in the way of XOR. Finally, the mixed chaotic sequence is constructed into the compressed sensing measurement matrix by means of cyclic shift. The experimental results show that the success rate of the reconstruction of the measurement matrix constructed by the algorithm is improved, and the PSNR of the measurement matrix is improved by about 12 dB when the compression ratio is less than 0.4.
Dual-detector system for Long-term tracking
HU Zhaohua, LI Qi, HAN Qing
2021, 38(9): 31-37.  
Abstract(53) HTML(20) PDF (1)
Abstract:
Aiming to solve the problem of target drift that occurs often in the process of long-term tracking, a dual-detector system for long-term tracking is proposed based on the spatially regularized correlation filters algorithm. In order to adapt to different tracking scenarios and increase the robustness of the model, SVM detector and siamese network detector are added, and the more efficient SVM detector is selected as the main detector. Only when the main detector fails to detect the target, the more accurate siamese network detector is started to detect the target. Through the cooperative work of the two detectors, the current image can be re-detected with high quality. At the same time, the adaptive spatial regularization term is also added in this paper, which can effectively suppress the influence of the boundary effect. The objective function is optimized by the alternating direction multiplier method to reduce the computational complexity and save running time. The experiment on datasets OTB-2013 and OTB-2015 show that the proposed algorithm has strong robustness in many characteristics. Especially in long-term tracking, the tracking distance accuracy and success rate of the proposed algorithm are improved by 12.9% and 6.2% respectively compared with the basic algorithm.
Stereo matching based on improved Census transform and color gradient fusion
LIU Jianming, HE Qing, CHEN Hui
2021, 38(9): 38-44.  
Abstract(38) HTML(18) PDF (3)
Abstract:
Aiming at the problem that the center point of the traditional Census transform window in stereo matching is easily affected by the external environment and the matching accuracy of some depth discontinuous regions is low, astereo matching algorithm based on improved Census transform and propagation filtering is proposed. In the initial matching cost calculation, the improved Census transform is fused with the color and gradient cost. At the same time, the propagation filter is introduced in the cost aggregation stage to maintain the edge of the parallax space image, which is not affected by the window size of the traditional local algorithm.Then, in the parallax processing part, the winner-takes-all(WTA) algorithm is used to calculate the initial parallax.In the following disparity optimization part, the method of left and right consistency detection and median filtering is used to obtain the final disparity map. Experimental results on Middleburry show that, compared with the traditional Census algorithm, the matching accuracy of the proposed algorithm is significantly improved, and the algorithm has good real-time performance and robustness.
Research on quality evaluation of spaceborne JPEG-LS lmage compression algorithm
LIU Xiangzeng, FAN Lijia, XU Xueling, XUE Jiepeng, MIAO Qiguang
2021, 38(9): 45-53.  
Abstract(54) HTML(29) PDF (6)
Abstract:
In order to evaluate the influence of on-board JPEG-LS compression algorithm on image quality, and provide technical support for the setting of on-orbit compression ratio, with the application of high-resolution multi-mode satellites as the background, the image compression evaluation model is built from two aspects: objective evaluation of compression quality of typical scene data and application effects of typical tasks. Through the analysis of objective indicators such as two-dimensional distortion, spectral distortion, and spatial distortion of image quality before and after compression, and comparison of typical application effects such as image classification, target detection, feature extraction and matching, which provides objective index statistical data and application effect comparison data support for the impact of compression algorithms on image quality, confirming that the algorithm can meet user needs. At the same time, it provides suggestions for users' specific application needs, and supports the rational distribution and expansion of the on-orbit image data market.
Combination of negative keywords spatial keyword query
JIN Hai, HAO Xiaoli, NIU Baoning
2021, 38(9): 54-60.  
Abstract(35) HTML(20) PDF (3)
Abstract:
Spatial keyword query oriented to personalized constraints is a hot issue in the field of database query, in which the rapidity and matching are the core issues to evaluate the merits of such query. The traditional spatial keyword range query is unable to match the query with personalized constraints except geographical location and keyword information, and the construction and update speed and query efficiency of most index structures in two-dimensional space are low. Aiming at these problems, puts forward a constraint with negative keywords (i.e., users don't like keywords) query model, USES the Geohash string representation point of interest object, built after the string sorting B+Tree as a binary Tree leaf nodes, through the binary Tree to filter object with negative keywords, to build a hybrid index structure based on Geohash BGIB-Tree. On this basis, the prefix matching search algorithm is designed based on the recursion of Geohash encoding. The pruning strategy is based on the region encoding and the object encoding prefix matching to quickly find the points of interest that meet the spatial constraints. Finally, the query can be completed by two-way search in the inverted index. By comparing with IR-Tree and BIR-Tree, the influence of BGIB-tree's construction time and related parameters on the query algorithm was verified on the real data set. The experimen tresults proved show that the index construction time was reduced by 30% and the query efficiency of the algorithm was improved by 29%.
Big data classification method of neighborhood search for online feature selection
LI Yueying
2021, 38(9): 61-66.  
Abstract(48) HTML(19) PDF (3)
Abstract:
In order to solve the problem of low efficiency of existing algorithms when dealing with massive data sets, a parallel big data classification method is proposed based on neighborhood search for online feature selection. In the Map phase, the big data set is divided into splits. And the dynamic unknown feature space is optimized by the firefly algorithm and simulated annealing algorithm, the neighborhood search is carried out for the online features, then selecting the best feature. The obtained feature set is used as the input feature of the Reduce stage, and then the kernel support vector machine is used to classify the data. Experimental results show that the proposed method is superior to other existing methods in terms of accuracy, recall, F value and time.
Research on four redundancy flight control computer with variable redundancy architecture
CHEN Xi, GAO Yang, QU Xi, WU Ming, FAN Guangtao
2021, 38(9): 67-73.  
Abstract(41) HTML(19) PDF (1)
Abstract:
As a key electronic product of space aircraft, flight control computer participates in the flight control of aircraft throughout the process, which has the characteristics of strong real-time performance, high reliability, radiation resistance and long life. A variable redundancy architecture four-redundancy computer technology is proposed, which combines the self-detection (BIT) technology and on-duty voting technology. It can realize different redundancy architecture management through fault detection, self-recovery, on-duty control, multi-mode voting and other technologies. Combined with the engineering practice, two four-redundancy architecture modes are analyzed from the system architecture of the flight control computer. Through the self-detection technology, the fault detection and location can be carried out quickly, and then the promotion and degradation management and reconstruction of the four-redundancy can be realized by the on-duty voting, and the reliability model can be established for the analysis. The reliability of four-mode parallel mode in 5 years (about 45, 000 hours) is as high as 0.995. The technology has been successfully applied to a space shuttle.
Design of a new floating point multiplier based on hybrid compression structure
YAO Shangshang, SHEN Li
2021, 38(9): 74-78.  
Abstract(53) HTML(22) PDF (3)
Abstract:
In order to further improve the performance of Floating-Point Multiplier and shorten the critical path delay of Floating-Point Multiplier, a hybrid compression structure based on new 4-2 compressor and 5-2 compressor is proposed. On the xc7a35tcsg324 development board of xillinx, the 32-bit Floating-Point Multiplier of IEEE754 standard is implemented based on this structure. Compared with the existing compression methods, the LUT resource and critical path delay are reduced by 45 and 0.004ns respectively. Compared with the traditional Floating-Point Multiplier, the critical path delay is reduced from 6.022ns to 4.673ns, which improves the performance of the Floating-Point Multiplier.
A gate-level placement and routing algorithm design for QCA circuits
KUANG Rui, PENG Fei, ZHANG Yongqiang, XIE Guangjun
2021, 38(9): 79-83.  
Abstract(41) HTML(24) PDF (3)
Abstract:
Quantum-Dot Cellular Automata (QCA) is considered asa promising solution to overcome the limitations ofconventional CMOS. Recently, the development of automated design tools for QCA circuits has attracted more and more attention from researchers, where the placement and routing algorithm is a critical step. The key issue of an algorithm design is the constraints of a clock scheme and clock synchronization. Agate-level placement and routing algorithm is proposed. The path information is pre-calculated and cached within the layout region constrained by the clock scheme, and the depth-first search strategy is applied to search for the correct circuit placement routing results. The algorithm is implemented in C++ programming language, and simulation results verify the correctness of the proposed algorithm.
A BNN accelerator based on time-sharing reuse row convolution LUT
DU Gaoming, CHEN Bangyi, WANG Xiaolei, LI Zhenmin
2021, 38(9): 84-92.  
Abstract(36) HTML(18) PDF (1)
Abstract:
The single-bit data width characteristic of Binary Neural Network (BNN) can tackle large-scale-data and huge-amount-calculation in Convolution Neural Network (CNN). In order to further accelerate the forward inference of BNN and reduce the required power consumption, a fully binarized neural network accelerator based on FPGA is proposed, in which the input image and edge padding are all binarized. And the accelerator skips the redundant calculations by reusing the Row Convolution LUT (RC-LUT) in a time-sharing way. By implementing on Xilinx's ZCU102 FPGA, this accelerator can achieve a Performance of more than 3.1 TOP/s, an Area Efficiency of 144.2 GOPS/KLUT, and a Power Efficiency of 3 507.8 GOPS/W.
Background calibration and FPGA implementation of comparator offset in SHA-less pipelined ADC
ZHAO Haonan, GUO Xuan, ZHOU Lei, WU Danyu, WU Jin
2021, 38(9): 93-98.  
Abstract(51) HTML(26) PDF (2)
Abstract:
In order to resolve the defect of comparator offset (including aperture error and static comparator offset) degrading the overall performance of high speed SHA-less pipelined ADC, an effective background digital calibration method is proposed. The detection of calibration is implemented by collecting the output residual voltage in digital domain, and the correction of calibration is implemented by controlling and configuring the DAC in analog domain. The calibration uses the difference of the mean values and the sum of extremums of the residueto characterize the aperture error and static comparator offset respectively, which avoids the disadvantages brought by other non-idealities in calibration, improves the ADC performance for high speed input, and improves the stability effectively.The proposed calibration method is applied in a 2.5 GS/s12bit ADC based on FPGA implementation. In this work, simulation and prototype verification are carried out to validate the practicability of the proposed method.The SNDR is improved by over 8dB@1.913GS/s based on the measurement. The calibration method decreases the difficulty of SHA-less pipelined ADC design, and relaxes the requirement of analog design, which provides reference for further high speed and low power ADC design.
A two-step approximation capacitance-voltage circuit design for gyroscope application
CHEN Chengying, WANG Yue, GAO Daifa, YING Jiayu, WANG Xiaoquan
2021, 38(9): 99-104.  
Abstract(42) HTML(18) PDF (7)
Abstract:
For Micro Electro Mechanical Systems (MEMS) gyroscope detection application, a two-stage capacitance-voltage (CV) circuit is presented. The input common-mode feedback technology is used to reduce the input common-mode voltage drift caused by parasitic and gain capacitors. Meanwhile, combined with correlated double sampling, compensation and holding capacitor technology, the two-step approximation voltage output is realized, which decrease the gain error, improves the frequency and accuracy of output signal. The circuit is fabricated by SMIC 0.18 μm 1P6M CMOS process. The post-simulation results show that in 3.3 V supply voltage, with 500 kHz clock frequency, the maximum signal frequency is 20 kHz, the C-V sensitivity is 12.4 mV/fF. Within 100 Hz bandwidth the dynamic range (DR) is 62.3 dB, and average power consumption is 3.85 mW.
The role of synchronization of CMOS neuronal circuitry in Noise suppression
WU Cuxia, ZHANG Peifeng, YANG Junjia, CHANG Xiaolong
2021, 38(9): 105-108.  
Abstract(41) HTML(18) PDF (4)
Abstract:
In order to analyze the effect of neuronal circuit coupling synchronization on noise suppression, a COMS neuronal circuit coupling network was constructed, and the synchronous discharge behavior of neuronal circuit coupling network was simulated by Hspice tool. The results show that the discharge frequency of single neuron circuit is greatly affected by noise, while the coupling synchronization of multiple neuron circuits can suppress noise interference and restore the original discharge frequency. Therefore, the synchronous discharge behavior of multiple neuron circuits can be used to encode the input signal to achieve reliable information coding.

Found in 1972
Monthly

Supervisor:
Xi'an Institute of Microelectronics Technology

Sponsor:
China Aerospace Science and Technology Corporation

ISSN 1000-7180

CN 61-1123/TN