Abstract: A multi-rate LDPC decoder, with memory efficient and low complexity, is presented in this paper based on the Min-Sum Algorithms. Mapping network, Address Generator and pipe line design are adopted to reduce the complexity of hardware implementation, decrease the quantity of memory usage, and enhance the throughout of system. The rate thus becomes reconfigurable through sharing resources without increasing any memory usage. Based on this structure, a LDPC decoder for CMMB standard is implemented on FPGA. The throughout can be up to 70.5Mb／s while the rate is 1／2 and iteration is 10, and 73.2Mb／s while the rate is 3／4 and iteration is 15.