Abstract: The implemention of scalar multiplication is described in the paper. The efficiency of module multiplication is improved by the combination of the multiplication process and the reduction process. Double interface RAM is used to accelerate the speed of data access. The capability of expansion is enhanced by the reserved RAM. The scalar multiplication module is synthesized with a library of synopays DC Z - 2007 03 solaris9 0.35 CMOS- technology and the result is about 18657 gates.