Abstract: Aiming at the scalability issue of evolvable hardware, partitioning truth table variable technique for digital circuit evolution is introduced. The method is to reduce the digits of inputs and outputs of the evolved system, that is to divide the intact target system which is evolved difficultly into several sub-systems which are evolved easily to evolve larger digital circuit. At the same time, multi-objective genetic algorithm is combined to optimize some parts of the circuit. Adder and Multiplier circuits are taken as examples. The experimental results prove that, by employing the proposed scheme, digital circuits can be designed with less resources and time delay more effectively in larger scale.