基于部分积优化的高速并行乘法器实现
Implementation of High-speed Parallel Multiplier Based on Optimized Partial Product
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摘要: 提出了部分积产生与压缩单元的改进结构,通过对部分积产生算法进行优化,采用选择器结构来替换传统的与或门,提高了部分积电路的性能,并降低了该模块的面积与功耗.对压缩单元的优化提高了部分积压缩的速度.对16×16并行乘法器综合验证表明,改进的乘法器性能提高14.5%,面积减少7.1%,同时功耗下降17.2%.Abstract: An improved architecture of partial product generation and compressing units is researched in this paper.By optimizing the partial product generating algorithm with multiplexers in stead of traditional AND and OR gates, the performance of partial product circuits is improved.Meanwhile, the area and power consumption of the module is also decreased.Optimized compressor units enhance the speed of partial product compression processing.The results of synthesis and verification for 16×16 parallel multiplier show that its performance was increased by 14.5%, as well as the area decreased by 7.1% and the power consumption reduced by 17.2%.
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