Abstract: An elastic buffer is designed to satisfy the need of clock domain crossing of the high-speed data flow based on the 10Gbase-KR ethernet protocol. Then the logical synthesis and gate-level simulation is conducted to demonstrate the design is correct. The elastic buffer is controlled with the normal half-full method, of which the depth is 16, the data transfer rate is 10Gbps, and the read-write clock frequency is 156.25MHz. By detecting the changes of the difference between the reading and writing address, it can make a contrast with the reading and writing speed and automatically insert or delete the IDLE characters. In the way, it can adjust the elastic buffer to realize clock frequency compensation and the clock domain crossing of the high-speed data flow correctly.