何星宏, 阴亚芳, 戴程. 浮点及整数混合运算器的设计与实现[J]. 微电子学与计算机, 2018, 35(2): 52-55, 60.
引用本文: 何星宏, 阴亚芳, 戴程. 浮点及整数混合运算器的设计与实现[J]. 微电子学与计算机, 2018, 35(2): 52-55, 60.
HE Xing-hong, YIN Ya-fang, DAI Cheng. Design and Implementation for a Integer-Float ALU[J]. Microelectronics & Computer, 2018, 35(2): 52-55, 60.
Citation: HE Xing-hong, YIN Ya-fang, DAI Cheng. Design and Implementation for a Integer-Float ALU[J]. Microelectronics & Computer, 2018, 35(2): 52-55, 60.

浮点及整数混合运算器的设计与实现

Design and Implementation for a Integer-Float ALU

  • 摘要: 针对现行普遍的浮点运算器耗费面积较大, 功能实现结构松散的问题, 设计实现一款浮点及整数混合运算器(Mixture-Arithmetic Logic Unit, M-ALU).该运算器基于基4算法华莱士树型结构, 并尝试一种新的阶码对齐方法, 合并整数运算与浮点运算处理逻辑.在三级流水线结构下可准确完成单精度浮点数, 扩展精度浮点数以及整数基本运算.采用基于synopsys提供的Design Compler综合工具在SMIC 65 nm工艺库下完成综合, 达到500 MHz主频.

     

    Abstract: For solve the issue that commont floating pointe ALU comsumes large area and srtucture loosely, a floating point and integer mixed operator M-ALU are designed and implemented. The algorithm based on the base-4 algorithm Wallace tree structure, and try a new order code alignment method, merging integer arithmetic and floating point arithmetic processing logic. In the three-stage pipeline structure can be accurately completed single-precision floating-point, extended precision floating-point and integer basic operations. Based on the synopsys provided by the Design Compiler synthesis tool in the SMIC 65nm process library to complete the synthesis, to 500 MHz frequency.

     

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