Abstract: A low cost double binary turbo decoder was presented in this paper, with a new architecture of interleaver used.Through the combination with the interleaver used in traditional scheme, this interleaver which is applied to the sliding window algorithm can reduce memory bank needed for interleaving and deinterleaving.Modulo normalization was also used to design the add-compare-select (ACS) module of the double binary turbo decoder for high clock rate and throughput.The verification, based on FPGA, indicates the proposed decoder can reduce the memory size by 12%, comparing with the traditional one, and 97%, comparing with the decoder uses ram to store interleaving/deinterleaving address.