Abstract: Simulation--based verification remains holding dominance in the verification of SoC and other sophisticated digital systems. The generating speed and distributing quality of stimuli are crucial factors in the convergence progress of verification. Coverage metrics quantitate how much the verification process has been completed. Coverage--directed and constrained- random stimulus generation methods have been proposed to improve the productivity and automaticity of the verification process. Constrained random stimulus generation techniques are categorized into two groups according to whether the structure information of the design under verification being used. In this paper, a survey is made on the state of art of the key technologies in simulation based verification of SoC in the following aspects: constraint definition, stimulus generation, coverage analysis, IP core and inter-- communication verification. And finally, the future trends and resarch directions are predicted.