Abstract: Deblocking Filter (DBF) is one of the components which have high computational complexity in HEVC decoder. Its processing speed directly affects the whole performance of video decoders. This paper proposes a high performance five-stage-pipeline-based hardware Architecture of DBF. In order to eliminate the influence of data dependency in the pipeline operation, a 16×8 pixels unit is chosen as basic processing unit. This unit occupies very little internal storage resources. The proposed hardware Architecture is implemented in Verilog-HDL. The implementation is synthesized by Xilinx ISE tool. The results show that the proposed architecture can meet requirement of real-time decoding 4 096×2 048@60fps high definition video under an operating frequency of 48.1 MHz.