Abstract: AMR (Adaptive Multi Rate) speech encoder have application in communication and multi media field widely for lower rate and higher quality.This paper presents a VLSI structure of “Audio DSP soft core + Hardware accelerator” based on AMR speech coding algorithm.This structure can complete encoder algorithm with meeting the demand of low cost and low power.The circuit can work steadily at 50MHz, and only have 50mW power and 78k chip area.This design was implemented on FPGA device, and the experimental results indicate that the structure is feasible.Meanwhile, as the design in this structure can also be applied in many other speech coding algorithms like G.7XX serial.