Abstract: A high speed read-out mechanism for OTP memory is proposed.The mechanism produces read control timing by its internal circuits.Address transition detection (ATD), pulse width modulation, control signal generation, sampling and latch modules are adopted in the proposed circuit, achieving good performance in simplicity, rapidity, accuracy, tolerance of noise and interference and low power consumption.Simulation shows that the entire reading period is merely 24ns and the read-out process can be completed stably and accurately without mistakes.