一种高效模(2n-2p)乘法器的设计
An Effective Architecture for Designing Modulo (2 n-2 p) Multipliers
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摘要: 结合两类修正方法，提出了一种高效的模(2n -2p)乘法器(n ≥ 2 p)的实现方法。与文献1中设计比较，本文乘法器结构上少了一级加法，并且综合结果也显示平均面积和延迟分别有10%和13%的减小。Abstract: In this paper,a new architecture is proposed to design modulo (2n -2p) multipliers on the condition n ≥ 2 p.When compared with the reference multipliers1, the proposed multiplier reduces both time delay and hardware requirements significantly. The proposed design is very suitable for VLSI implementation. It can be completed in one cycle.
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