Abstract: A novel interpolation architecture implemented in FPGA chip based on halfband filter is presented in this paper. This architecture, which utilizes the characteristic of halfband filter and the technique of algebraic transformation, has reduced the computation complexity and the requirement to coefficient bit wide. Meanwhile, the ways of decreasing filter order with multistage interpolation are also introduced. By considering area-speed tradeoffs, the number of multiplication elements is reduced to the least. Comparing with the traditional method, the practical design achieves expected design performance with much 1ess logic resource usage.