Abstract: In order to promote the large-scale application of FPGA computation, a micro architecture of FPGA based on dynamic partial reconfiguration mechanism is designed and implemented. The architecture provides a set of user-development mode that can improve the development efficiency of FPGA, which can support SIMD/MIMD parallel computing mode in FPGA, and supports pipeline mode through communication of reconfigurable units. The experimental results show that the architecture can effectively simplify the user's programming mode while maintaining the high performance and low power consumption of FPGA computing system.