Abstract: According to the gain compression mechanism, interstage residue amplifiers of pipelined ADC(Analog to Digital Converter) would generally cause nonlinear distortions, which could be reasonably modeled as odd-order power series. Effect and weight of the interstage gain nonlinearity on the overall quantization accuracy are defined and characterize. A digital background calibration technique is then proposed for post nonlinearity correction using estimated coefficient of the model, which would be adaptively identified employing second-order cross-correlation information with digital pseudo-random sequence added into the signal path. Simulations are performed for a 14-bit Pipelined ADC with three stages. Assuming the first two 5-bit stages both have third-order nonlinearity corresponding to a gain compression of 5% at full scale, results show that with this calibration scheme, SFDR and SNDR are improved from 67.84dB、51.26dB to 94.16dB、72.97dB respectively high-resolution pipelined ADC designs would benefit much from the error analysis conclusion and technical solution proposed in the paper.