Abstract: Spread spectrum clocking is an effective solution to reduce the electromagnetic interference produced by digital chips, using a clock signal with a frequency that is intentionally swept (frequency modulated) within a certain frequency range, with a predefined modulation profile. A 10 GHz spread spectrum clock generator (SSCG) is realized by a fractional-N frequency synthesizer with a third-order delta-sigma modulator. We accomplish the spread spectrum function by changing the divider ratio. The SSCG integrates a conventional PLL, a digital 3^rd order MASH 1-1-1 delta-sigma modulator and an address generator. The SSCG generates clocks at 10 GHz, a 5000×10^-6 down spread with a triangular waveform frequency modulation of 30.525 kHz. This SSCG has been fabricated in a 55nm CMOS process, and it consumes 20 mW from a supply of 1.2 V. The EMI reduction is 29.3 dB and the simulated phase noise is -110 dBc/Hz at 1 MHz offset.