王文, 桑红石, 沈绪榜. 存储单元抗TID/SEL电路加固技术面积代价研究[J]. 微电子学与计算机, 2014, 31(6): 25-29.
引用本文: 王文, 桑红石, 沈绪榜. 存储单元抗TID/SEL电路加固技术面积代价研究[J]. 微电子学与计算机, 2014, 31(6): 25-29.
WANG Wen, SANG Hong-shi, SHEN Xu-bang. Study on the Memory Cell TID/SEL Hardening by Design Technology Area Cost[J]. Microelectronics & Computer, 2014, 31(6): 25-29.
Citation: WANG Wen, SANG Hong-shi, SHEN Xu-bang. Study on the Memory Cell TID/SEL Hardening by Design Technology Area Cost[J]. Microelectronics & Computer, 2014, 31(6): 25-29.

存储单元抗TID/SEL电路加固技术面积代价研究

Study on the Memory Cell TID/SEL Hardening by Design Technology Area Cost

  • 摘要: 在太空辐射环境中,总剂量辐射(Total Ionizing Dose,TID)效应和单粒子闩锁(Single Event Latch,SEL)效应严重影响存储器的可靠性.由此讨论了存储单元TID效应和SEL效应的原理,探讨了基于电路的加固技术(RHBD),设计了4种新的抗TID/SEL存储单元加固方案,并和现有几种方案进行对比,研究了这些加固方案的面积代价.研究结果表明,抗TID/SEL RHBD方案普遍会使存储单元的版图面积增加87.5%以上.提出了一种加固方案,可以在加固性能和面积代价上得到较好的折衷.

     

    Abstract: In space radiation environment, total ionizing dose (TID) effect and single event latch (SEL) have serious impact on the reliability of memory devices. Total Ionizing Dose effect and Single Event Latch and radiation hardening technologies were discussed, especially the Radiation Harden by Design hardening technologies. Four types of new TID/SEL tolerable memory cells are designed to compare the area cost with the available designs. The results show TID/SEL tolerable memory cell design generally increases the cell area by 87.5% at least. One of the proposed programs could make a good trade-off between the hardening performance and the area cost.

     

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