高速DDR3存储控制器的时钟偏差控制和优化
Design and Optimize Clock Skew for High-speed DDR3 Memory Controller
-
摘要: 基于65 nm工艺, 完成了高性能海量处理器芯片中的高速DDR3存储控制器的物理设计.重点介绍了DDR3存储控制器物理设计中的布图布局设计和时钟树设计, 并针对EDA工具自动生成时钟树导致的DDR3 PHY域内总线时钟偏差较大问题, 提出并实现精确手动干预关键时钟路径上的时钟树设计优化方法, 并进一步采用寄存器逻辑优化方式, 成功将DDR3 PHY域内总线时钟偏差控制在30 ps内, 满足设计要求的性能.Abstract: In this paper, we finish the physical design of DDR3 memory controller in a high-performance and massive data processor chip base on 65 nm process. The paper presented the floorplan and clock tree synthesis of DDR3 memory controller. Due to the biggish bus skew of DDR3 PHY, we recommended the precise manual intervention to clock tree of the critical clock path and made the logical registers optimization. The bus skew of DDR3 PHY was controlled less than 30ps successfully.
下载:
