Abstract: This article designs the ARINC429 bus protocol IP core based on FPGA.The integrated design and the operational principle of the IP core are given.With modular method,this design integrates the data protocol processing module,the data buffer module and timing module in one FPGA chip.Using the independent methods and synchronization ways of designing the encoder and decoder,it improves the reliability and lessens the interference between the data efficiently,and resolves the metastability issue.The validating result indicates that the functions of IP core could fit the designing demand.Through physical testing at last,the IP core can achieve every function and could be applied in series of situation.