Abstract: In a system, applications with different security requirements need selection among algorithm SHA-256, SHA-384, SHA-512. However, these types of algorithms were implemented in hardware separately in current studies. In this paper, a VLSI architecture for the SHA-2 family is proposed, in order to meet the needs of different options. The proposed architecture supports a multi-mode operation in the sense that it performs all the three hash functions (256,384,512) of the SHA--2 standard. The proposed system is compared with the implememation of each hash function in FPGA device. The results show that the frequency of the introduced system can be achieved 74MHz, while the area of the implement only increase 40% over SHA-256 and basically the same as SHA-384/512.