Abstract: This paper presents an easy-approached assertion-based verification (ABV) method by embedding assertions in source codes to monitor key function spots of the design during simulation.This method is approached by five steps.As an application example, a case study of functional verification for a UART RTL model, using System Verilog Assertion (SVA) to describe the properties, is provided.The studied result shows that the new method is feasible and can be applied in the design and verification process to increase the observability of the design.