基于FPGA的图像卷积IP核的设计与实现
Design and Implemenation of FPGA-based Convolution IP Core for Image Processing
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摘要: 提出了一种基于FPGA的卷积运算IP核的设计方法.充分利用FPGA的并行体系架构和丰富的块存储资源采用规则的模块化的设计方法并兼顾可扩展的原则完成了二维图像卷积IP核的设计, 实现了实时图像卷积运算中卷积窗口大小和卷积系数的灵活调整.这种新的卷积IP核在充分节约硬件资源的前提下很好地满足了实际的应用, 使得卷积运算在图像处理应用中更加灵活方便.Abstract: We present a new 2-D convolution IP core for real-time image processing taking advantage of the feature of convolution.Thanks to FPGA′s parallel structure and rich memory resource this design does well in modularity and expandability and the convolution′s window size and cofficients can be changed flexibly.Beside satisfying practical applications the new IP tries it′s best to save hardware.It makes convolution more flexible and convenient.
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