文婧媛, 徐欣锋. 基于CORDIC算法的高速可配置FFT的FPGA实现[J]. 微电子学与计算机, 2010, 27(3): 24-28.
引用本文: 文婧媛, 徐欣锋. 基于CORDIC算法的高速可配置FFT的FPGA实现[J]. 微电子学与计算机, 2010, 27(3): 24-28.
shu
WEN Jing-yuan, XU Xin-feng. A FPGA Realization of CORDIC Based High Speed Variable Point FFT[J]. Microelectronics & Computer, 2010, 27(3): 24-28.
Citation: WEN Jing-yuan, XU Xin-feng. A FPGA Realization of CORDIC Based High Speed Variable Point FFT[J]. Microelectronics & Computer, 2010, 27(3): 24-28.
shu

基于CORDIC算法的高速可配置FFT的FPGA实现

A FPGA Realization of CORDIC Based High Speed Variable Point FFT

    摘要
  • 摘要: 论述了一种用于星载合成孔径雷达 (SAR) 星上数据实时自主处理系统中的高性能FFT的FPGA实现.采用CORDIC算法实现复数乘法, 降低了系统的复杂性, 提高了运算速度, 并提出一种新型便捷的旋转因子产生方法, 无需额外的ROM资源.采用块浮点的数据类型, 有效避免了大点数FFT的溢出问题.运算点数可配置, 能够实现64~32k点, 实部、虚部均为16bit数据的FFT运算.整体设计采用16点并行流水结构, 提出了适用于16通道并行读写的无冲突地址产生方法.最高工作频率可达118.89MHz, 100MHz频率下, 1024点FFT的计算时间仅为4.48μs, 完全满足高速实时的运算要求.

     

    Abstract: Present a FPGA realization of high performance FFT used in star-carried synthetic aperture radar real-time data processing system.The Coordinate Rotational Digital Computer (CORDIC) algorithm is adopted to realize complex multiplication, reducing the system complexity and saving hardware resource.A new convenient twiddle factor generator is proposed and don't need extra ROM resources.The block floating point data type effectively solves the overflow in long point FFT.The point can be varied from 64 to 32K and the real and imaginary parts of data are 16 bits.The whole design uses 16-point parallel pipeline structure.A 16-access parallel conflict free address generation is proposed.The highest clock frequency is 118.89MHz.The processor can compute a 1024-point FFT with 4.48μs, satisfies the requirement of high speed, real-time operation.

     

    • HTML全文
    • 参考文献(0)
    • 相关文章
    • 施引文献
  • 资源附件(0)

/

返回文章
返回