Abstract: In this paper,a SoC (system on chip) design of five-ports Tri_speed Ethernet switch controller IP is introducted,and the implementation of the key modules in the design is described.This paper present a shared buffer architecture based on scatter/gather DMA which can satisfy the requirements of high bandwidth and low latency of the data flow in Ethernet.The design has been verified on FPGA and the result proves that it can reach the non_blocking wire_speed switching performance of 930.5Mbps at lower consumption,and the physical design of the IP has been implemented.