吕坚, 李华, 周云, 王璐霞, 蒋亚东. 高性能CMOS采样保持电路的设计[J]. 微电子学与计算机, 2010, 27(3): 140-143,147.
引用本文: 吕坚, 李华, 周云, 王璐霞, 蒋亚东. 高性能CMOS采样保持电路的设计[J]. 微电子学与计算机, 2010, 27(3): 140-143,147.
shu
LV Jian, LI Hua, ZHOU Yun, WANG Lu-xia, JIANG Ya-dong. High Performance CMOS Sample and Hold Circuit[J]. Microelectronics & Computer, 2010, 27(3): 140-143,147.
Citation: LV Jian, LI Hua, ZHOU Yun, WANG Lu-xia, JIANG Ya-dong. High Performance CMOS Sample and Hold Circuit[J]. Microelectronics & Computer, 2010, 27(3): 140-143,147.
shu

高性能CMOS采样保持电路的设计

High Performance CMOS Sample and Hold Circuit

    摘要
  • 摘要: 设计了一种基于0.5μmCMOS工艺的高线性、高精度、高速的采样/保持电路.采用一种仅由4个PMOS管、一个电容和一个NMOS开关构成的新型双边信号采样开关, 有效地提高了双边信号采样电路的线性度并减小了电路的噪声和失调.仿真结果表明:输入摆幅为1V的156kHz的双边信号, 在10MS/s的采样速率下, 其无杂散动态范围 (SFDR) 为120dB.

     

    Abstract: A high linearity, high resolution and high speed sample/hold circuit is proposed.A novel low distortion switch is proposed, which is composed of four PMOS transistors, one capacitor and one NMOS switch.It can directly sample a bipolar signal and increase the sampling linearity with low noise and distortion.This circuit achieves a 120dB SFDR when sampling a 1V peak-to-peak, 156kHz bipolar signal under 10MS/s sampling rate.

     

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