Abstract: A 10-bit,50-Ms/s low power ADC is presented in this paper by using a pipelined architecture of 1.5bit perstage. The capacitors used in the each pipeline stage are scaled down, which results in significant power savings. Furthermore, a novel slew rate boost circuit is proposed in this paper to save the power of the OTA. The whole ADC was designed in TSMC 0.18μm CMOS process. The SNR of the ADC is 59dB when the input signal frequency is 20MHz. The differential and integral non-linearity (DNL and INL) are within ±0.4 and ±0.5 LSB respectively, as well as the total power consumption is about 47mW.