李冬冬, 杨军. 并行AES算法加密解密电路的高效实现[J]. 微电子学与计算机, 2015, 32(3): 100-103.
引用本文: 李冬冬, 杨军. 并行AES算法加密解密电路的高效实现[J]. 微电子学与计算机, 2015, 32(3): 100-103.
LI Dong-dong, YANG Jun. Efficient Implementation of Parallel AES Algorithm Encryption and Decryption Circuit[J]. Microelectronics & Computer, 2015, 32(3): 100-103.
Citation: LI Dong-dong, YANG Jun. Efficient Implementation of Parallel AES Algorithm Encryption and Decryption Circuit[J]. Microelectronics & Computer, 2015, 32(3): 100-103.

并行AES算法加密解密电路的高效实现

Efficient Implementation of Parallel AES Algorithm Encryption and Decryption Circuit

  • 摘要: 介绍了AES算法的基本原理,为了在加密和解密过程中轮操作能够共用,结合算法的结构特点,设计了等效的轮操作结构,使用迭代的方式设计了通用的AES算法加密解密电路结构,通过外部输入信号控制其工作在加密或解密状态,整个加密解密系统电路由6个AES算法核并行组成,以提高算法处理速度.综合仿真结果显示,系统电路时钟频率为177.9 MHz,处理速度达到5.69 Gb/s.

     

    Abstract: The basic principles of AES algorithm is introduced in this paper. In order to share the same round operation in encryption and decryption process, an equivalent round operation structure is employed based on the structural characteristics of the algorithm. A general circuit structure of AES algorithm is designed by using iteration method, decided whether to work as encryption or decryption by control signal. The whole encryption and decryption system circuit is composed of 6 AES algorithm cores in parallel to increase throughput. The simulation result shows the clock frequency is 177.9 MHz and the throughput achieves 5.69 Gb/s.

     

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