Abstract: The Time-Sensitive Networks (TSN) provides important network technology support for "Made in China 2025" plan. The design and implementation of the Time Aware Shaper (TAS), the fundamental mechanism of TSN, is of great significance. In this paper, based on the multi-core network processor, we propose a method for quantifying the bandwidth into time slots and design the function module structure and the processing flow of the TAS mechanism. Moreover, for the problem of time slot length variation caused by the error between the CPU clock and the PTP (Precision Time Protocol) clock, we propose a protection band adjustment algorithm to correct the time slot of the port. Finally, we develop the TAS mechanism based on the Cavium multi-core network processor. The experimental results show that the TAS mechanism can send packets according to the pre-allocated time slots. Besides, enabling the protection band adjustment can effectively correct the time slot error and increase the robustness of the TAS mechanism.