万志江. 基于FPGA的DDS IP核的研究与设计[J]. 微电子学与计算机, 2013, 30(8): 98-102.
引用本文: 万志江. 基于FPGA的DDS IP核的研究与设计[J]. 微电子学与计算机, 2013, 30(8): 98-102.
WAN Zhi-jiang. Research on DDS IP Core Based on FPGA[J]. Microelectronics & Computer, 2013, 30(8): 98-102.
Citation: WAN Zhi-jiang. Research on DDS IP Core Based on FPGA[J]. Microelectronics & Computer, 2013, 30(8): 98-102.

基于FPGA的DDS IP核的研究与设计

Research on DDS IP Core Based on FPGA

  • 摘要: 针对传统的用单片机和 DDS 芯片设计高频信号发生器的方法具有的硬件结构复杂、人机交互性差和低可移植性等问题,提出了一种实现高频信号发生器功能的直接数字频率合成器(DDS)IP 软核的设计方法。本设计首先通过加权的方法实现十进制向二进制的转换,提高 IP 核的人机交互性,并引入 streamlined 算法在 FPGA 上实现频率控制字产生单元,解决传统设计中硬件结构复杂的问题。然后,在 ISE 设计平台上采用 Verilog HDL 硬件描述语言进行 DDS 行为描述,连接频率控制字产生单元,实现一个可重载的 DDS IP 软核。最后,在 XILINX SEED XDTK V5实验平台上对 IP 核进行板级验证。验证结果表明,此 IP 核具有良好的人机交互性和可移植性,能够很好的满足实际应用。

     

    Abstract: According to the complexity of hardware structure, the poor human-computer interaction and low portability in designing a high frequency signal generator by MCU and DDS chip,a direct digital frequency synthesis (DDS) IP soft-core which has a function of high-frequency signal generator is designed.In order to improve the human-computer interaction, we convert decimal to binary by the method of weighted, and use streamlined algorithm to create the frequency control word so that we can solve the complexity of hardware structure in the traditional way. Meanwhile, Verilog HDL hardware desiption language is applied to realize the DDS behavior description and achieve an overloaded DDS IP core on the ISE platform.At last,the board-level verification of the IP core is developed on the XILINX SEED XDTK V5 platform.It is demonstrated experimentally that the IP core can satisfy the practical application with a good human-computer interaction and high portability.

     

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