Abstract: We present a design of write back strategy for distributed register file in VLIW digital signal processor to solve the synchronization problem of branch pipeline and write back signals. The design includes generating execution cycles,write back signal register and write back control unit.We assess the area and power of the design. The proposed strategy can fully implement the advantage of distributed register file, will save 50% in power compared with central register file,and will save 70% in area compared with traditional write back control method.