Abstract: Register Transfer Level (RTL) -based VHDL Simulator is proposed and implemented, named RVS.The RVS's flow, composition modules as well as their functions is described.Firstly, the RTL subset of VHDL language in RVS is defined.Furthermore, a top-down syntax analysis algorithm based on recursion is developed during the compilation phase.During the simulation phase, an event-driven schedule algorithm based on process is proposed with debugging functions.We give the implementation of RVS in Windows OS and Visual Studio 2003.Finally, the experiment and analysis show that the compiler and simulator of RVS perform well and produce encouraging solutions correctly on two SAP-CPU designs controlled by combinational logic and micro-program.