Abstract: This paper presents a design of 2-D DCT IP soft core based on Loeffler′s algorithm. We make use of the shifter and addition operations to replace the multiplication operations. In order to save hardware resources, the multiplication factors are coded by CSD, and the technology of 1-D DCT reusing is taken; In order to improve the circuit speed, the pipelining technology is taken, and optimize the transposed matrices is adopted. Based on abovementioned algorithms the IP soft core with Verilog HDL is obtained. For the IP soft core, we made the compiling, synthesis, layout and post simulation, so the correctness of the design is verified. The experiment shows that design has a maximum frequency of 139.43 MHz, which can satisfy the requirement of real-time video image compression.