一种采用斩波-稳零技术的低功耗Delta-Sigma调制器的设计
The Design of Low-Power Delta-Sigma Modulator Utilizing Chopper-Stabilization Technique
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摘要: 采用TSMC 0.18μm CMOS混合信号1P6M工艺实现了一种应用于信号检测系统的低功耗Delta-Sigma调制器.该调制器采用单环积分器级联反馈(CIFB)结构降低了电路的复杂度,并采用Chopper-Stabilization技术降低了系统的直流失调和1/f噪声,提高了电路的低频特性.调制器采用1.8V电源电压,整体功耗仅为2mW,版图尺寸1.25×1.3mm2.仿真结果表明,该调制器在50kHz信号带宽范围内,可以达到92dB的信噪失真比,99.3dB的动态范围和15bits的有效位数,满足传感器信号检测系统的要求.Abstract: A low-power Delta-Sigma modulator for system of signal detection is presented,which is implemented in TSMC 0.18μm 1P6M CMOS mixed-mode signal process.The modulator adopts structure of Cascaded of Integrator FeedBack (CIFB) for low complexity and chopper-stabilization technique for improvement of dc-offset and 1/f noise characterization.The power dissipation of modulator is 2mW at supply of 1.8V,the dimension of whole layout is 1.25×1.3 mm2.The post-simulation of modulator shows that 92dB SNDR and 99.3dB SFDR and 15bits ENOB have been achieved within bandwidth of 50 kHz.The modulator is suitable for signal detection system of sensor.
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