应欢, 王雷欧, 薛志远, 王东辉, 侯朝焕. 面向具有VLIW结构DSP的汇编级翻译的方法[J]. 微电子学与计算机, 2014, 31(9): 20-23.
引用本文: 应欢, 王雷欧, 薛志远, 王东辉, 侯朝焕. 面向具有VLIW结构DSP的汇编级翻译的方法[J]. 微电子学与计算机, 2014, 31(9): 20-23.
YING Huan, WANG Lei-ou, XUE Zhi-yuan, WANG Dong-hui, HOU Chao-huan. An Assembly-level Translation Scheme Towards a VLIW DSP[J]. Microelectronics & Computer, 2014, 31(9): 20-23.
Citation: YING Huan, WANG Lei-ou, XUE Zhi-yuan, WANG Dong-hui, HOU Chao-huan. An Assembly-level Translation Scheme Towards a VLIW DSP[J]. Microelectronics & Computer, 2014, 31(9): 20-23.

面向具有VLIW结构DSP的汇编级翻译的方法

An Assembly-level Translation Scheme Towards a VLIW DSP

  • 摘要: 为了简化不同体系结构间代码迁移工作,提出一种面向具有超长指令字架构的数字信号处理器的汇编级翻译的方法.前端分析将汇编代码中的指令信息同语义映射为机器无关的中间表示.采用路径探测法移除分支指令延迟槽构建指令流图,并重构源程序控制流图.基于各条指令的时间戳分配和指令间的数据依赖关系分析,移动代码和修改时间戳来线性化并行代码.实验证明,该方法能够正确翻译汇编程序.

     

    Abstract: To simplify code migration between different architectures,an assembly translation solution towards a very long instruction word Digital Signal Processor is presented in this paper.Based on the front-end analysis,valid instructions in assembly files are mapped to machine-independent representation.Through path detection method,the delay slots are eliminated and the instruction flow graph is built,based on which the control flow graph is reconstructed.Additionally,by allocating the timestamp for each instruction,and analyzing data dependency among execution-packet,the linearizing pipelined operation is accomplished by movement and timestamps modification of instructions.The experiment indicates that the assembly programs were correctly translated to the target architecture.

     

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