嵌入式GPU中二级高速缓存的设计与实现

Design and Implementation of Embedded GPU Cache Controller

摘要: 针对嵌入式GPU与主存之间进行数据交互时出现速度不匹配的问题, 设计了一种适用于嵌入式GPU的二级高速缓存Cache控制器.二级Cache控制器采用四路组相联的映射结构, 使用伪最近最少使用(Pseudo_LRU)替换算法, 可以管理16~512 kB的二级高速缓存.实验结果表明, 当选取Cache大小为128 kB时, Cache的命中率达到71.12%.

Abstract: A suitable for embedded GPU cache controller is designed for the speed mismatch problems data interaction between main memory and embedded GPU. The cache controller adopts a four-way set associative mapping structure, uses pseudo-Least Recently Used replacement algorithm. The size of CacheSRAM can be configured, which configuration range is 32~512 kB. The experimental results show that when the CacheSRAM capacity is 128 kB, hit rate of the graphics application's Cache can reach to 71.12%, the cache controller can further enhance the overall performance of embedded GPU.