55nm工艺下SoC漏电功耗优化方法研究
Leakage Power Optimization Based on 55 nm Technology SoC Design
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摘要: 随着工艺节点快速演进到深亚微米,芯片设计的复杂度大幅增加,高性能低功耗的构架逐渐成为主流设计要求.尤其是工艺发展到65nm及以下时,漏电功耗开始极速增大,在高性能要求不变的同时,要兼顾低功耗需求,这对芯片设计人员是个巨大的挑战.以55nm工艺的SoC设计为例,通过多阈值电压优化漏电功耗的方法,在芯片物理设计阶段,对设计的漏电功耗进行优化,使得设计性能和功耗满足需求.Abstract: As the process node gets smaller and complexity of IC design increase,low power and high performance designs become more popular.The big challenge lies in achieving a high performance design with power optimization.In this paper,we demonstrate leakage power optimization using Multi-Vt techniques,to both low the leakage power and achieve the high performance design.
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