Abstract: This paper presents a 12 bit SARADC for a system of digital Power Factor Correction. The questions about parasitic capacitor of DAC module have been analyzed and solved using a new architecture which is 1-6-5 capacitor segments. A pseudo-differential method is used to eliminate charge injection and degrade clock feed-through in order to improve the ADC. This design has been tape out using 0.35 μm CMOS process. Simulation results show that the SNR and the SFDR of this design are about 6% higher than those of 6-6 segment with a 50 kHz sinusoidal input under a 0.98 MHz sampling rate.