浮点矩阵向量乘法的FPGA设计与优化
Design and Optimization of Floating-Point Matrix-Vector Multiply for FPGAs
-
摘要: 提出了一种基于IEEE-754的32 bit、64 bit浮点数格式，二叉树数据流（binary tree data flow）的矩阵向量乘法器。其在FPGA上流水线和高度并行化的高效执行。以Altera公司的EP2C70为实现设备，研究了设计的硬件规模，时钟速度，和峰值GFLOPS能力。Abstract: In this paper,we design a matrix-vector multiplier which is based on IEEE-754 (32 bit,64 bit) floating point data formats,and the binary tree data flow.The implementation in FPGA platform is pipeline and highly efficient parallel.With Altera EP2C70 as the target device,detailed study of the design of the hardware size,clock speed,capacity and peak GFLOPS.
下载:
