Abstract: According to the applications and requirements of QC-LDPC encoding decoding chip,a structure of length rate-variable QC-LDPC encoding decoding chip is proposed in this paper,and the hardware is implemented.An encoder based on cyclic shift matrix vector multiplier and a decoder based on partly-parallel cyclic iterative decoder structure are included in this chip.The assessment of the chip shows that the encoding decoding chip with this structure has excellent performance,low implementation complexity and high data throughput.On this basis,the QC-LDPC encoding decoding chip is conducted a logic synthesis and layout design.Layout area of the chip is 15mm².Features and performance of the chip meet the design requirements.