Abstract: In order to reduce the high complexity of the traditional SoC design method, this paper presents the design, synthesis and simulation flow of the Rijndael arithmetic IP Core using high level synthesis (HLS) technology. A hardware-oriented coding style and its optimization scheme specifically for the Rijndael arithmetic is also studied and designed. Through a comparison with a traditionally designed IP Core, the IP Core designed by HLS technology outperforms in nearly all respects, with a significantly reduced design complexity, which greatly proves the advantage of HLS.