Abstract: The method to reduce the CMOS power during the physical design stage is disucssed in this paper, utilizing the SoC instance of an image processing design.Firstly, the placement locations of the PAD and macro cells were adjusted and the power planning was optimized.As a result, an intermediate layout with lower voltage drop is gained, which reduces the CMOS power indirectly.Secondly, the file of switching activity ratio planned and the power optimization instructions set are applied on the intermediate layout, and the CMOS power is directly reduced.Finally, simulation results show that the method has saved the power 10.92%.The SoC instance chip entity has passed the test on the ATE and the power meets the design expection.