Abstract: This paper depicts a data width transfer buffer design that interfaces physical layer with link layer of embedded SATA2.0 host bus adapter (HBA) system which based on Xilinx Virtex-5 FPGAs.For the purpose of eliminating the disorders from data transferring, the logical circuit, which is composed of multi-bit shift register group, defined between physical layer and upper layers has been simulated and board level verified.Compared with the existing Xilinx FIFOs, the design's average latency is reduced by 70 percent.Resultsshow that the asymmetric buffer can save more chip resources and control logic under the same throughput capability.