基于Balsa-Xilinx FPGA的异步设计流程
Asynchronous Design Flow Based on Balsa-Xilinx FPGA
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摘要: 针对异步电路设计工具问题,提出了一种基于Balsa和Xilinx FP(iA的全异步设计流程.采用Balsa语言描述异步设计产生网表,导入网表在Xilinx下生成可配置文件,达到板级验证并进行布局布线后仿真分析,在完成异步电路设计的同时采用同步EDA工具验证,以实现异步设计与同步软件的结合,最后通过八位异步全加器设计实例验证该异步设计流程的可行性.Abstract: This paper proposes a full asynchronous design flow based on Balsa and Xilinx FPGA for asynchronous circuit design tools.The asynchronous circuit is described in the Balsa language to generate corresponding net list file,and a configurable file can be obtained by importing the netlist into Xilinx FPGA.With downloading the configurable file into FPGA chip,the board-level verification and post-place & route are achieved.Thus,both asynchronous design and verification in synchronous EDA software contact successfully.Finally,the feasibility of the asynchronous design flow has been proved by the design example of 8-bits asynchronous full-adder.