Abstract: In order to improve the speed and power consumption of the binary multiplier, this paper present a high-quality 33×28 binary multiplier with modified radix-4 Booth encoding and improved partial product circuits in partial product generator and a 7:3 compressor in partial product compression module. Compared with the multiplier created by Synopsys' module compiler, the speed of proposed partial product generator has improved 34%, the time of compressor has reduced about one 3 : 2 compressor's delay by combining 7:3 compressors with other compressors and the total delay of proposed multiplier has improved 17.70% at 0. 9 V on a TSMC 90 nrn process technology.