一种基于余数系统的奇偶检测算法及VLSI实现
Parity Detection Algorithm and VLSI Implementation Based on the RNS
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摘要: 提出了一种基于常用三模基2n+1,2n-1,22n+1改进的奇偶检测算法,此方法仅使用一个n位的模加器,一个n+1位的进位选择加法器(CSA),一个2n位的比较器及一些简单的组合单元即可实现,有效节省了资源,并简化了设计的复杂度.当n=30时,面积仅为6130.958μm2,延迟仅为0.67ns.Abstract: A parity checker based on triple-mode2n+1,2n-1,22n+1is proposed in this paper,this checker only need a n bit adder,a n+1 bit CSA adder,a 2n bit comparator and some simple combination unit,it lowers the resource consumption and simplifies the design effectively.When n=30,an area of only 6130.958μm2,the delay is only 0.67ns.