王新胜, 韩良, 刘海龙, 喻明艳. 纳米工艺下考虑缓冲器传热效应的集成电路互连线温度分布模型及缓冲器插入位置优化分析[J]. 微电子学与计算机, 2013, 30(12): 41-46.
引用本文: 王新胜, 韩良, 刘海龙, 喻明艳. 纳米工艺下考虑缓冲器传热效应的集成电路互连线温度分布模型及缓冲器插入位置优化分析[J]. 微电子学与计算机, 2013, 30(12): 41-46.
WANG Xin-sheng, HAN Liang, LIU Hai-long, YU Ming-yan. Integrated Circuit Interconnect Wire Temperature Distribution Model Considering Buffer Heat Transfer and Buffer Location Optimization Analysis under Nanometer Process Condition[J]. Microelectronics & Computer, 2013, 30(12): 41-46.
Citation: WANG Xin-sheng, HAN Liang, LIU Hai-long, YU Ming-yan. Integrated Circuit Interconnect Wire Temperature Distribution Model Considering Buffer Heat Transfer and Buffer Location Optimization Analysis under Nanometer Process Condition[J]. Microelectronics & Computer, 2013, 30(12): 41-46.

纳米工艺下考虑缓冲器传热效应的集成电路互连线温度分布模型及缓冲器插入位置优化分析

Integrated Circuit Interconnect Wire Temperature Distribution Model Considering Buffer Heat Transfer and Buffer Location Optimization Analysis under Nanometer Process Condition

  • 摘要: 分析了温度对互连线上缓冲器插入的影响,提出了考虑介质、通孔和缓冲器传热效应的互连线温度分布模型.基于此模型使用45 nm互连工艺参数计算了单层和多层互连线的温度分布.结果显示,考虑缓冲器传热时多层互连中局部互连线温度受缓冲器影响不大,全局互连线温度受缓冲器影响显著,与介质传热模型相比温度降低超过10摄氏度.温度变化对缓冲器插入位置有显著影响,利用提出的互连线温度模型,在衬底温度梯度分布、1.5 mm互连线长和单个缓冲器插入条件下,与均匀插入缓冲器相比,位置变化幅度超过10%.

     

    Abstract: This paper analyzes the impact of temperature on the interconnect buffer insertion,and proposes an interconnect temperature distribution new model considering the dielectrics,vias,and buffers heat transfer effect. Single and multi-layer interconnect temperature distributions are calculated using 45 nm process parameters based on the new model.The results show that the local interconnect line temperatures are affected a little by buffer heat transfer,while the global interconnect lines are subject to significantly affected and lower 10 degrees Celsius than the dielectric heat transfer model.Moreover,the temperature has a significant effect on buffer insertion locations. Considering the substrate temperature gradient distribution, the location changes more than 10% compared to uniform buffer insertion under 1.5 mm interconnect wire length.

     

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