Abstract: In this paper, a second order ΔΣ Time-to-Digital Converter (TDC) is proposed to achieve high resolution and wide signal bandwidth. The proposed TDC is a single-loop architecture based on a time-domain error-feedback filter using time-domain arithmetic circuits such as time registers, time adders and so on. Implemented in SMIC 28 nm CMOS process, spectre simulation results shows the noise floor of the TDC by taking the minimum PSD value of 84 dBps²/Hz which corresponds to a 50Msps classical quantizer without noise shaping and with 1.5 ps steps. The TDC power consumption depends on the time difference between input edges, typically about 1.24 mW for 1ns interval measurement, the measurement range can be up to 7.5 ns.