多通道数字助听器算法及低功耗VLSI设计
Algorithm Research and Low-power VLSI Design of a Multi-channel Digital Hearing Aid
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摘要: 改进了多通道数字助听器中的听力补偿和噪声消除算法,并进行了低功耗VLSI设计.听力补偿方面,提出一种改进的多通道宽动态范围压缩(WDRC)算法;该方法降低了存储和计算开销,并抑制了对残余背景噪音的过度放大.噪声消除方面,利用语音谱和噪声谱的帧间相关性,改进了传统的多子带谱相减算法,使之在硬件实现时便于并行运算,同时不影响消噪性能.最后,综合采用多种低功耗设计方法,在SMIC的130nm工艺条件下,完成了基于上述算法的多通道数字助听器VLSI设计.后仿结果表明,该设计总功耗仅为228μW.Abstract: The hearing compensation algorithm and noise reduction algorithm in multi-channel digital hearing aids were studied in this paper,and a low-power VLSI design according to these algorithms was implemented further.On hearing compensation,a new multi-channel Wide Dynamic Range Compression(WDRC) algorithm was proposed,which can not only reduce the cost of storage and calculation.On noise reduction,by considering the correlation between adjacent frames of speech spectrum and noise spectrum,the traditional multi-band spectral subtraction algorithm was modified for parallel operation in hardware implementation,without degrading the performance.The low-power VLSI design of a multi-channel digital hearing aid based on the proposed algorithms was realized in SMIC 130nm process.The post-simulation power dissipation of the system is only 228 μW.
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